Search results

This study aims to describe the behavior of blocks in the system under consideration using systems modeling language (SysML) state machine diagrams. In this paper, formalization and model checking for SysML state machine diagrams have been investigated.

The work by Zhang and Liu (2010) proposed a formalization of SysML state machine diagrams in which the diagrams were translated into CSP# processes that could be verified by the state-of-the-art model checker PAT. In this paper, several modifications have been made and new rules have been added to the translation described in that work.

First, three translation rules were modified, which apparently are inappropriately defined according to the SysML definition of state machine diagrams. Next, we add new translation rules for two components of the diagrams – junction and choice pseudostates – which have not been dealt with previously. Further, we are implementing the automatic translation system on a web-based model-driven development tool, which reflects on our translation rules.

As the contribution of this work, more reasonable verification results for more general SysML state machine diagrams can be achieved.